A Prolog based approach towards the recognition of logic functional blocks in CMOS circuits is described in this thesis. A transistor level description of the circuit is assumed to be available. Predefined gates and logic blocks are extracted from such a description. This recognition procedure is a step towards raising the level of description of a network. An extracted block level description can be used to verify the correctness of the implemented logic. The approach described here uses a circuit partitioning technique to divide a given circuit into smaller subcircuits. This is followed by the extraction of logic expressions at the output nodes of subcircuits. From these logic expressions, gates are recognized. Functional blocks in the circuit are recognized based on rules which define such blocks in terms of their structural configuration.

Master of Science