For a few decades, CMOS has been well known for a quite efficient design methodology. With its unique characteristics, CMOS logic has been most commonly used for low voltage operation. Although in many cases CMOS logic can achieve more robust performance than pass-transistor logic and Dynamic Logic counterparts, due to the fact that the delay o f low voltage CMOS has been degraded significantly, it is unpractical in many applications. So a novel logic family called dual mode logic (DML) which can be switched between static and dynamic operation modes with a clock control signal is introduced. In the dissertation I introduce the basic DML circuit structure as well as the operation. DML gates present the advantages o f both static and dynamic gates, so DML gates allow these gates to achieve ultra-low power while operating in the static mode, and also high performance in the dynamic mode. The task is to analyze the typical DML gates and study their properties in comparison with conventional ones. And possible application in full adder design is studied; the simulation shall be conducted under different supply voltage and signal frequency, and simulation results will be analyzed and compared.

Master of Science (Electronics)