
Three 12 bit, 40 MS/s pipelined analog-to-digital-converters (ADCs) are developed in 0.35μm CMOS process with 3.3V single power supply. The proposed ADCs architectures study the influence of the amplifier sharing technique in the power consumption and the main performances in the pipeline ADCs. Simulations results with extracted netlists are provided and show that the amplifier sharing technique has potential to be used in the reduction of the power consumption.
This work has been partially supported by Ministerio de Educación y Ciencia of Spain (TIN2006-15460-C04-04).
Amplificadores analógicos, Convertidores digitales
Amplificadores analógicos, Convertidores digitales
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