Switching activity evaluation of CMOS digital circuits using logic timing simulation
Juan-Chico, J.; Bellido, M. J.; Ruiz-de-Clavijo, P.; Baena Oliva, Carmen; Jiménez Fernández, Carlos Jesús; Valencia-Barrero, M.;
Switching activity evaluation of CMOS digital circuits using logic timing simulation
The degradation delay model is applied to accurately estimate the switching activity in CMOS digital circuits. The model overcomes the limitations of conventional gate-level logic simulators to handle the propagation of glitches, a main source of switching activity. Model results of a four-bit multiplier are within 4% with respect to HSPICE, while Verilog overestimations are up to 68%.
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These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
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This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
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