A 350 µW 2.3 GHz integer-N frequency synthesizer for body area network applications

descriptionPublicationkeyboard_double_arrow_right Conference object 01 Jan 2011 English Publisher:Institute of Electrical and Electronics Engineers (IEEE)

Authors: Masuch, Jens; Delgado-Restituto, Manuel;

handle: 10261/83832

A 350 µW 2.3 GHz integer-N frequency synthesizer for body area network applications

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Abstract

This paper presents a low power integer-N synthesizer with an output frequency of 2.3 GHz. The complete PLL has been integrated in a 90 nm CMOS technology and operates from a 1 V supply voltage. The synthesizer has been optimized for power consumption by employing an efficient quadrature VCO and a phase-switching prescaler. It achieves a phase noise of -121 dBc/Hz @3MHz while consuming only 350 μW in the PLL core. The typical reference spur level is about -40 dBc.

This work has been supported by the Spanish Ministry of Science and Innovation under grant TEC2009-08447, the Junta de Andalucía under grant TIC-02818 and the 2007- 2013 FEDER Program.

Conferencia celebrada en Phoenix (EE.UU) del 17 al 19 de Enero del 2011.

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