High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology

descriptionPublicationkeyboard_double_arrow_right Conference object 01 Jan 2001 Spain English Publisher:Institute of Electrical and Electronics Engineers (IEEE)

Authors: Río Fernández, Rocío del; Rosa Utrera, José Manuel de la; Medeiro Hidalgo, Fernando; Pérez Verdú, Belén; Rodríguez Vázquez, Ángel Benito;

handle: 10261/3768 , 11441/89402

High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology

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Abstract

We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use only 16 oversampling ratio. Especial emphasis is placed on technology issues, namely: poor analog performance and substrate coupling. The measured performances are 13-bit dynamic range operating at 2MS/s and 12-bit dynamic range operating at 4MS/s. The modulator consumes 77mW from a 3.3-V supply and occupies 1.32 mm2.

Comunicación presentada al "ICECS 2001" celebrado del 2 al 5 de Septiembre del 2001 en Malta.

This work has been supported by the ESPRIT Project 29261 MIXMODEST.

Peer reviewed

Country

Spain

Related Organizations

University of Seville
Spain

Keywords

Analog-to-digital converters, ADSL application

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