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doi: 10.1049/el:19980270
handle: 11441/77558 , 10261/3743
This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of the DAC than those previously reported, thus enabling the use of very simple analog circuitry with neither calibration nor trimming required.
Comisión Interministerial de Ciencia y Tecnología TIC97-0580
High-speed ADC, Multi-bit ΣΔ modulator
High-speed ADC, Multi-bit ΣΔ modulator
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