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This paper presents a low-power, low-noise microsystem for the recording of neural local field potentials or intracranial electroencephalographic signals. It features 32 time-multiplexed channels at the electrode interface and offers the possibility to spatially delta encode data to take advantage of the large correlation of signals captured from nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information. This effectively increases the system dynamic range and avoids the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro with cellular cultures of primary cortical neurons from mice. The system shows an integrated input-referred noise in the 0.5-200 Hz band of 1.4 μVrms for a spot noise of about 85 nV /√{Hz}. The system draws 1.5 μW per channel from 1.2 V supply and obtains 71 dB + 26 dB dynamic range when the artifact-aware auto-ranging mechanism is enabled, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios.
Design, Chopper instrumentation amplifier, LFP, Mice, Electric Power Supplies, Circuit, system-on-chip, Animals, time multiplexing, artifact-aware, Electrodes, auto-ranging, 65 nm cmos, Neurons, Cancellation, Amplifiers, Electronic, biomedical electronics, neural recording, correlated double sampling, Signal Processing, Computer-Assisted, Equipment Design, Interface, CMOS integrated circuits, spatial delta encoding, ECoG, Artifact-aware, Power, Stimulation, offset reduction loop, Mode, neurophysiology, Noise, Artifacts, Algorithms
Design, Chopper instrumentation amplifier, LFP, Mice, Electric Power Supplies, Circuit, system-on-chip, Animals, time multiplexing, artifact-aware, Electrodes, auto-ranging, 65 nm cmos, Neurons, Cancellation, Amplifiers, Electronic, biomedical electronics, neural recording, correlated double sampling, Signal Processing, Computer-Assisted, Equipment Design, Interface, CMOS integrated circuits, spatial delta encoding, ECoG, Artifact-aware, Power, Stimulation, offset reduction loop, Mode, neurophysiology, Noise, Artifacts, Algorithms
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