Low noise frequency synthesizers and PLLs are a critical part of both wireless and wireline communication infrastructure. As data rates continue to increase in the datacenter and in consumer devices such as Wi-Fi networks, the PLL jitter requirements are becoming increasingly strict. The first work explores a digital-sampling PLL based on a noise-shaping SAR (NS-SAR) analog-to-digital converter (ADC). This breaks the quantization noise limitation of prior ADC based PDs and enables a lower resolution ADC quantizer and CDAC to be used. Additionally, this improved ADC resolution reduces the PD gain requirement and improves the lock performance. The 2nd-order noise-shaping of the NS-SAR ADC improves the time-to-voltage resolution of the phase detector by reducing in-band quantization noise and ADC input-referred noise. The second work explores a sub-sampling PLL with saturated feedback to improve the frequency lock capability of the high-gain sub-sampling phase detector. A multiplexer passes only a single VCO edge to the phase detector reducing the likelihood for the PLL to lock to the wrong multiple of the reference due to phase detection ambiguity. Additionally, since the multiplexer is only passing a window for the VCO edge to pass, the noise of the divider becomes less critical.