Noise-Shaping SAR (NS-SAR) ADCs have become prominent in modern precision and low-power data acquisition applications due to their ability to achieve higher resolution with very low hardware overhead. This thesis focuses on breaking the resolution-bandwidth tradeoff in NS-SARs by pushing the noise transfer function (NTF) to higher order. 1) We introduce a new residue filter configuration for higher-order NTF with improved robustness. 2) We interleave NS-SAR quantizer in a 3rd-order hybrid-loop delta-sigma modulator (DSM) to expand the bandwidth. 3) We propose a NS-SAR quantizer with filtering capability to enable a 3rd-order high-resolution VCO-based continuous-time (CT) DSM loop with a small area. The first work is a cascaded NS-SAR architecture that increases the system order to 4th order and enables more effective noise shaping for higher signal-to-noise ratio (SNR). The proposed architecture enhances the robustness of high-order noise shaping at the system level and is inherently process, voltage and temperature (PVT) stable. A two-phase settling technique improves the noise-power efficiency of the residue amplifier. The prototype was fabricated in 28-nm CMOS, occupies 0.02 mm2 and consumes 120μW. The measured Signal to Noise and Distortion Ratio (SNDR) over a 100-kHz bandwidth is 88dB, resulting in a Schreier Figure of Merit (FoM) of 177 dB. The second work is a hybrid-loop DSM architecture with a bandpass time-interleaved (BP TI) NS-SAR quantizer. With increased throughput and the use of complex conjugate NTF zeros, the quantizer helps increase the system order to 3rd-order and increase the effective bandwidth. The prototype DSM with a BP TI NS-SAR quantizer is built in 28-nm CMOS and occupies a die area of 0.09 mm2. The measured peak SNDR is 67.5 dB for a 100-MHz BW. The total power consumption is 13.4mW at a sampling rate of 1.6 GS/s. The resulting Schreier FoM of 166.2 dB. The third work is a VCO-Based CTDSM with a 2nd-order NS-SAR quantizer for a 3rd-order NTF with simple loop dynamics. An anti-aliasing filter (AAF) enables the time-domain output from the VCO integrator to be directly sampled by the voltage-domain quantizer. The 28nm CMOS prototype CTDSM achieves 84.2dB SNDR and 86.8dB DR within a 1MHz bandwidth while consuming 1.62mW at 100MS/s. The core circuit occupies only 0.024mm2. No calibration or coefficient tuning is required.