Integrating MDG variable ordering in a VHDL-MDG design verification system

Name: Integrating MDG variable ordering in a VHDL-MDG design verification system
Creator: Feng, Yi
Keywords: Traduction automatique de VHDL, Vérification de propriétés, Vérification formelle, Ordonnancement des variables, Intégration de logiciels, Graphes de décision multidirectionnels

Feng, Yi

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https://dx.doi.org/10.71781/11...

Thesis . 2001

Data sources: Datacite

Integrating MDG variable ordering in a VHDL-MDG design verification system

descriptionPublicationkeyboard_double_arrow_right Thesis 01 Jan 2001Embargo end date: 29 Sep 2023 English Publisher:Université de Montréal

Authors: Feng, Yi;

doi: 10.71781/11014

Integrating MDG variable ordering in a VHDL-MDG design verification system

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Abstract

Thèse numérisée par la Direction des bibliothèques de l'Université de Montréal.

Keywords

Traduction automatique de VHDL, Vérification de propriétés, Vérification formelle, Ordonnancement des variables, Intégration de logiciels, Graphes de décision multidirectionnels

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