The continuous demand for larger and more complex sensors constantly drives the need for smarter, faster, and more powerful silicon. To make these technologies more accessible to power sensitive applications, careful implementation of power management needs to occur. This is especially true of Two Dimensional Sensor Arrays (TDSA). Each pixel in a TDSA has several subcomponents, all of which need to be designed to carefully optimize power. As the pixels increase incomplexity and generate more and more data, the data management portions need to scale as well. This thesis documents the design iterations and analysis of the data management logic for a medium scale two dimensional array of sensors. The examined sensor has five 16-bit registers of data that needs to be moved from the sensor measurement logic to an IO port for external processing. Various architectures for both the data management blocks, as well as their sub components were designed in Verilog, synthesized to transistors and simulated for power measurements. The conducted experiments show that the Row Shift-Pass multiplexing architecture provides a significant reduction in power over a traditional Single Shift Chain. Digital designers can use this information to create more power efficient and higher performance sensors to meet the needs of an evolving world.