With the fast development of big data, Internet of Things (IoT), and edge computing, the memory systems are required to the highest ever, in which the performance and energy efficiency have significant impacts on the overall system capability. Three things about SRAM make it ideal for on-chip storage and cache memories, It features high read and write speeds, low dynamic power consumption for reading and writing, and a mature process. In this paper, we give an all-encompassing review of low-power SRAM design techniques, including circuit-level and architectural innovations along with the emerging Computing-In-Memory (CIM) paradigm. Techniques include novel circuit methodologies such as read/write-assist, as well as emerging transistor technologies like GAA nanosheets. This survey reviews techniques to reduce the dynamic and leakage power consumption, enhance writability and reliability in low-voltage operation, and minimize the energy overhead associated with data movement. This work systematically investigates conventional and emerging methods and offers insights into how to design energy-efficient SRAM for next-generation portable and AI-centric platforms.