Abstract Machine learning-based prediction techniques have emerged as an effective solution for early estimation of VLSI design parameters, reducing the need for repeated synthesis and simulation operations. This work presents a machine learning-based framework for predicting power consumption, silicon area, and propagation delay using synthesis-oriented hardware datasets. The proposed approach employs Linear Regression, Decision Tree, Random Forest, and a combined DT+RF model using hardware-related input features including bit width, gate count, and flip-flop count. The models are trained on a dataset generated from Cadence Genus synthesis of both combinational and sequential digital circuits. Validation was performed using 8-bit, 16-bit, and 32-bit Arithmetic Logic Units (ALUs) and Up-Down Counters synthesised on the TSMC 180 nm technology library. Comparative analysis demonstrates that Decision Tree achieved the highest prediction accuracy, while Random Forest provided superior generalisation capability. The combined DT+RF model offered a balanced trade-off between accuracy and robustness. The proposed framework enables rapid early-stage VLSI parameter estimation and significantly reduces design exploration time. Keywords VLSI, Machine Learning, Power Estimation, Area Prediction, Delay Analysis, Cadence Genus, Decision Tree, Random Forest.