Name: Hypervisor Extension for a RISC-V Processor
Keywords: FOS: Computer and information sciences, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, 64-bit RISC-V processor, Hardware Architecture (cs.AR), Microprocessadors, Virtual computer systems, Hypervisor extension, Computer Science - Hardware Architecture, Microprocessors, Accelerators

descriptionPublicationkeyboard_double_arrow_right Article , Preprint , Conference object 01 Jan 2023Embargo end date: 01 Jan 2024Publisher:arXivJournal:2023 RISC-V Summit Europe

Authors: Gauchola Vilardell, Jaume; Costa Prats, Juan José; Morancho Llena, Enrique; Canal Corretger, Ramon; Carril Gil, Xavier; Doblas Font, Max; Otero Calviño, Beatriz; +4 Authors

doi: 10.48550/arxiv.2406.17796

arXiv: http://arxiv.org/abs/2406.17796

handle: 2117/414131

Hypervisor Extension for a RISC-V Processor

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Abstract

This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.

This work is partially supported by the DRAC (IU16-011591), the HORIZON Vitamin-V (101093062) and the Computación de Altas Prestaciones VIII (PID2019-107255GB) projects.

Peer Reviewed

Related Organizations

Universitat Polite`cnica de Catalunya
Spain

Keywords

FOS: Computer and information sciences, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, 64-bit RISC-V processor, Hardware Architecture (cs.AR), Microprocessadors, Virtual computer systems, Hypervisor extension, Computer Science - Hardware Architecture, Microprocessors, Accelerators, Sistemes virtuals (Informàtica)

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