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</script>We present N2Net, a system that implements binary neural networks using commodity switching chips deployed in network switches and routers. Our system shows that these devices can run simple neural network models, whose input is encoded in the network packets' header, at packet processing speeds (billions of packets per second). Furthermore, our experience highlights that switching chips could support even more complex models, provided that some minor and cheap modifications to the chip's design are applied. We believe N2Net provides an interesting building block for future end-to-end networked systems.
Accepted at SysML 2018
FOS: Computer and information sciences, Computer Science - Machine Learning, Computer Science - Distributed, Parallel, and Cluster Computing, Hardware Architecture (cs.AR), Distributed, Parallel, and Cluster Computing (cs.DC), Computer Science - Hardware Architecture, Machine Learning (cs.LG)
FOS: Computer and information sciences, Computer Science - Machine Learning, Computer Science - Distributed, Parallel, and Cluster Computing, Hardware Architecture (cs.AR), Distributed, Parallel, and Cluster Computing (cs.DC), Computer Science - Hardware Architecture, Machine Learning (cs.LG)
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