Driven by 5G and AI, the semiconductors’ speed increases, density increases, pad-pitch decreases, chip-size increases, and power dissipation increases. All these provide challenges (opportunities) to advanced packaging technology such as the heterogeneous integration (HI), which uses various packaging technologies to integrate dissimilar chips, photonic devices, or components (either side-by-side, stack, or both) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes, and companies into a system or subsystem. For the next few years, we will see more of a higher level of HI, whether it is for time-to-market, performance, form factor, power consumption, signal integrity, and/or cost. In this presentation, the HI will be defined and it is classified into 5 categories, namely, HI on organic substrate, HI on TSV-interposer substrate, HI on TSV-less interposer substrate, HI on fan-out RDL-substrate, and HI on ceramic substrate. The trends of substrate for HI will also be discussed.