ABSTRACT Flip-chip integrated circuits packaged on organic ball grid array (BGA) substrates have steadily gained in popularity in recent years. New applications with larger die and substrates, usually application specific integrated circuits (ASICs) or microprocessors, are under evaluation throughout the industry. Second-level reliability data for these assemblies are scarce. This paper describes the results of a board-level reliability study of W.L. Gore's Via on Chip Pitch organic substrate. Two substrate versions were used––standard and variable coefficient of thermal expansion (VCTE). The VCTE substrate was designed to reduce the substrate CTE under die area to more closely match that of the die. Substrate design and fabrication are described. Using an assembly process developed at Gore, 18.5mm nonfunctional, flip-chip die with over 2800 I/O were soldered and underfilled atop 42.5mm substrates. 1763 eutectic solder spheres (a 42 by 42 array) on a 1mm pitch were attached to the substrates to make the BGA packages. Finished packages were mounted onto printed circuit boards. First-and second-level assembly process flows will be outlined and critical factors discussed. There were seven testable BGA nets on each package, each consisting of a daisy chain defining a complete row around or under the die. Testable nets were located in a region that modeling indicated would see the highest stress during testing. Assemblies were tested at 0-100C (air-to-air) for 10,000 cycles, with net resistance readings every 500 cycles. The resistance changes of the two substrate types was compared to evaluate the impact on board level reliability. The test setup is described, resistance changes are presented, and test results are correlated to modeling data.. Parts are examined post 10,000 cycles using scanning acoustic microscopy (SAM), cross-sectioning, and scanning electron microscopy (SEM). Condition of the BGA solder joints after cycling is presented.