This article discusses edge detectors implemented in programmable logic controllers. The behaviors of different vendors’ solutions are presented with pros and cons. The trigger functions defined in the IEC 61131-3 standard were analyzed for implementations. The main contribution of this paper is an idea for hardware acceleration of standard trigger functions that enables us to build single-clock-cycle edge detectors. Additionally, the structure for automatic edge detection on every input is shown. The structure with a synthesizable Verilog HDL description is presented. The comparison of the solution with vendor programmable logic controllers (PLCs) proves the effectiveness of the designed hardware-aided unit.