Abstract The application of the Industrial Ethernet brings up issues of both the reliability and behaviour of the networks under a demanded load, while preserving the permitted time delay in the whole network. We propose an algorithm that designs the network topology, which meets the required fault tolerance and allows reliable communication between the parts of the control system. For this purpose, we employ an iterative genetic algorithm that designs the physical topology and verifies the behaviour under the expected load and time delay in the whole network. We propose the chromosome representation and genetic operators required. The network results compare physical topologies, which were acquired by a common algorithm and by our algorithm.