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https://doi.org/10.31219/osf.i...
Article . 2022 . Peer-reviewed
License: CC BY
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Design and Implementation of Half Adder, Full Adder and CMOS Full Adder

descriptionPublicationkeyboard_double_arrow_right Article , Preprint 10 Dec 2022Publisher:Center for Open Science
Authors: Furqan Hameed;

doi: 10.31219/osf.io/uqa9m

Design and Implementation of Half Adder, Full Adder and CMOS Full Adder

Abstract

In this paper, 1 bit full adder is designed in Microwind and DSCH. It is analysed using different implementation methods like AOI logic and using transmission gates. It is converted into an equivalent RC model to make the model simpler but less accurate for calculations. However, accurate results are obtained and verified using DSCH, Verilog code and Mircrowind.

Keywords

Engineering, Electrical and Electronics, Electrical and Computer Engineering

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
0
Average
Average
Average
hybrid