This thesis describes the main works undertaken to explore the feasibility of exploiting the memristor to improve the linearity of the ADC (i.e., integral non-linearity (INL), differential non-linearity (DNL), signal-to-noise-and-distortion ratio (SNDR), and spurious-free dynamic range (SFDR)). A memristor-assisted background calibration scheme has been proposed. Its functionality and efficacy have been demonstrated in Nyquist successive-approximation-register ADCs (SAR ADCs) with a resistive digital-to-analog converter (RDAC) and a capacitive DAC (CDAC). The complete circuitry is designed in a standard 180 nm and 65 nm Bipolar-CMOS-DMOS (BCD) process. The memristor model used for the circuit design was developed from a physical in-house fabricated memristor and validated in Cadence virtuoso simulation tools. At the end of the research, the proposed calibration scheme is able to calibrate a 100 kS/s 12b SAR ADC’s SNDR from 49.40 dB to 63.70 dB, with a total ADC area of 0.08 mm2 in 180 nm process, and a 5 MS/s 12b SAR ADC’s SNDR from 46.23 dB to 66.10 dB, with a total ADC area of 0.0153 mm2 in 65 nm process. To the best of the author’s knowledge, this is the first research on the memristor-assisted background calibration scheme for ADCs. As a feasibility study, this research is still at the initial stage, which means there are a lot of design challenges and limitations, making this emerging scheme is not yet competitive compared with the state-of-the-art ADCs with conventional CMOS calibration schemes. With the reported results, the author would like to draw attentions of the ADC design community to an alternative calibration scheme enabled by the emerging technology. The author expects the ADC performance will improve in the near future as the emerging CIM device technology (not only the ”memristor”) is advancing rapidly.