The complex interrelationships between technology, design, and fabrication require that radiation-hardness must be considered when circuits will be used in low-orbit or deep-space environments. Unlike traditional synchronous circuits, asynchronous circuits do not use a global clock signal to control the update of the state registers and have potential benefits including enabling soft-error tolerance with low overhead. The traditional method to design digital circuits, including asynchronous circuits, utilizes a Hardware Description Language (HDL) such as Verilog, that includes variable assignments, explicit notations to express concurrency and control flow structures. However, HDLs have been compared to assembly languages because of their low level of abstraction, explicitly describing the structure of the circuit in detail. In contrast, Chisel is a modern hardware construct language (HCL) that provides a more abstract description of digital circuits and is part of a synthesis framework that automatically produces lower-level Register-transfer level (RTL) circuit descriptions.This dissertation proposes a synthesis framework aimed at generating novel Radiation Hardened by Design (RHBD) asynchronous circuits from Chisel specifications using novel timing and soft-error tolerant control templates and a RHBD mutual exclusion element to support arbitration. Specifying these designs in Chisel enables scalability and reusability by reducing the non-recurring engineering costs of design, test, and verification. We demonstrate the utility of this flow on a design case study of an asynchronous network on chip (ANoC) that is part of an accelerator for fully homomorphic encryption. Two different RHBD templates, the traditional Triple Modular Redundant (TMR) and the timing resilient template were used to explore different ANoC designs. The resulting layouts show that timing resilient design is 2.46x smaller than the more traditional TMR counterpart. Our flow highlights the potential benefits of asynchronous circuits, not just for soft-error tolerance, but also for modularity, reusability, and composability.