Processing-In-Memory (PIM) architectures have recently gained significance because of their capability of addressing the memory-wall problem in an effective and efficient manner. The components used in the communication mechanism and interconnection of multiple PIM nodes have more stringent requirements of area and power efficiency over components used in traditional interconnection networks. Firstly, the performance and implementation metrics of a communication mechanism for the Data-IntensiVe Architecture (DIVA), which is a PIM system, using an off-chip interconnection network approach are reported. The novelty of this PIM-to-PIM communication scheme arises from its implementation via a parcel mechanism in an extremely area, power and performance efficient manner.