A small but persistent signal in wafer slot order was observed at functional test, affecting logic yield. Through wafer slot Randomization at several operations in the route a process step within high-k metal gate formation was suspected to be causing the degrade, but conventional approaches did not reveal the root cause. By combining datamining with a thorough analysis of sector and electrical data we identified a defect mechanism exacerbated by the delay between gate metal and polysilicon deposition. By applying a process change, we addressed the issue and achieved yield improvement.