Abstract : This report documents an effort to determine the feasibility of constructing a realistic fault set for a given analog microcircuit from the information provided by a microcircuit yield simulator program. A methodology for this was developed and demonstrated using a simple PMOS process. The fault set which was generated demonstrates that it is possible to define how process defects affect electrical performance through the use of high level circuit models. The fault set can be ranked by probability of occurrence, and is suitable for use by a circuit simulation program.