In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.