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IEICE Electronics Express
Article . 2010 . Peer-reviewed
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Novel FPGA-based pipelined floating point FFT processor

Authors: Li Wei; Wang Jun;

Novel FPGA-based pipelined floating point FFT processor

Abstract

Two novel architectures for pipelined floating point fast Fourier transform on FPGA are presented. The new radix-22 two-path delay feedback (R22TDF) architecture leads to 50% area saving for floating point complex adders compared with the radix-22 single-path delay feedback (R22SDF) architecture. Besides a new hybrid architecture is presented which mixes the R22TDF and R22TDF butterfly structures and is flexible and efficient for FPGA implementation.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
0
Average
Average
Average
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