Second-Order Generalized Integrator -- Frequency-Locked Loop (SOGI-FLL) is a popular technique available in the grid synchronization literature. This technique uses gain normalization in the frequency locked-loop. This increases the computational complexity. In this paper, we propose an alternative implementation to reduce the computational complexity of the SOGI-FLL. The proposed implementation modifies mainly the frequency locked-loop part and requires normalized voltage measurement. dSPACE 1104 board-based hardware implementation shows that the proposed implementation executes 20% faster than the standard implementation. This could be very beneficial for high switching frequency application e.g. >= 1MHz. In addition to the nominal frequency case, multi-resonant implementation is also proposed to tackle grid harmonics using a~simpler harmonic decoupling network. Small signal dynamical modeling and tuning are performed for both implementations. Dynamical equivalence is also established between the two implementations. Experimental comparative analysis demonstrates similar or better performance (depending on test scenarios) with respect to the standard implementation of the SOGI-FLL.