This thesis examines the suitability of reconfigurable logic devices for the implementation of real-time embedded systems. Hybrid hardware systems have been studied, differentiated according to the method of hardware integration (either intraprocessor, bus-based or coprocessor). Software support and reconfigurability were found to be important considerations for the success of the systems. Most are aimed at high performance computing. Traditionally, Field-Programmable Gate Arrays (FPGAs) have been characterised as a sea of gates. The modern trend has been found to be towards more coarse-grained architectures - with hard cores, such as multipliers and processors included within the FPGA fabric. Research systems extend this concept even further. The issues and techniques used in real-time systems and real-time operating systems (RTOSs) have been examined. Reconfigurable devices have been found in real-time systems but the interaction between computation being executed in both hardware and software components has not been studied. Some researchers have moved some RTOS components into hardware in order to improve the predictability of the resulting systems. The verification of systems through techniques such as deadline monotonic analysis (DMA) is examined, along with some practical considerations. Suitable tools for designing reconfigurable embedded systems have been analysed. System-level design tools were examined - these were found to not be suitable for modern FPGA-based embedded systems. Traditional co-design tools were also evaluated - again, these were not intended for use in reconfigurable systems. Techniques used in embedded design with modern FPGAs has been summarised. In order to evaluate the suitability of a new technology to a particular application, suitable metrics need to be chosen. For this thesis, the metrics chosen are execution time, real-time metrics (interrupt latency, worst-case execution time), power and area usage. This is followed by an overview of the experimental work conducted, including the evaluation of applications and architectures in the context of real-time embedded systems. These applications, Finite Impulse Response (FIR) filtering and Least Mean Squares (LMS) adaptive filtering, are examined, along with possible solutions in a general sense. A range of architectures are defined, specifically targeted at providing solutions for the applications at hand. Hardware cores designed for input and output of analogue data are presented. Cores for the measurement of execution times and interrupt latency are also shown. The specific solutions for the applications are then shown, including entirely software-based solutions, those using hardware cores for all computation and those using both software and hardware for portions of the computation. A novel configurable network is described, which allows the software to control the configuration of components in the hardware system. This network allows the hardware cores to perform processing without interference from the software. All systems employ the uClinux operating system running on the Xilinx Microblaze processor. Each of the systems has been evaluated according to the metrics described. The results of these evaluations are presented, showing that interrupt latency is unrelated to CPU utilisation. The addition of computational hardware effectively lowers CPU utilisation, although at the expense of increased idle power consumption. The hardware cores are found to be significantly more power efficient, consuming between 9% and 75% less power than equivalent software solutions. A new equation is derived for the worst-case response time of hybrid hardwaresoftware tasks, based on deadline monotonic analysis. This equation shows that hybrid tasks should offer significant real-time performance advantages, where task-level paralellism can be exploited. Real-time performance is improved through the use of Real-Time Applications Interface (RTAI) real-time extensions, reducing interrupt latency by a factor of 20. The configurable network system is found to provide superior performance, along with reduced power consumption at the expense of 0.1% additional hardware over the base system.