As voice and data communications networks proliferate, they face ever increasing demands for reliability, portability, and bandwidth. In many applications, the transmitted power is limited by practical considerations. Examples include satellite, cellular, and undersea long haul fiber communications systems. In these applications Forward Error Correction (FEC) techniques may be used to achieve reliable communications within the constrained power. FEC techniques are ultimately limited in their performance by the conflicting requirements of high speed, high computational complexity, and low size and power consumption. VLSI implementations of the elegant and powerful Viterbi convolutional decoding algorithm (VA) [1], which uses a recursive parallel search computation, are limited by the massive intra- and inter-chip communications requirements between nodes of the search graph. This constraint limits the number of states (nodes of the VA graph), for high-speed applications, and hence the overall performance of the VA. Current high speed single chip VLSI implementations are limited to a convolutional constraint length of about 7 and therefore require 27=128 processing nodes. Incrementing the constraint length by one provides nearly an order of magnitude improvement in BER [2], but requires twice as many computational and communications resources -- beyond the capabilities of a single chip. This size constraint limits single chip VLSI implementations to a coding gain of ~7dB. Strong motivation exists for using longer constraint length codes, requiring several decoding ICs. A multi-chip VLSI VA implementation is impractical for high speed applications due to the inter-chip communications bottleneck. The approach discussed in this paper overcomes this limitation by employing free-space optical interconnects to provide the required inter-chip connection, while maintaining on-chip speeds between chips.