Security agencies have recently emphasized their concerns about the validity and trustability of mission critical chips fabricated overseas. These concerns originate from the non-securable conditions of the fabrication facilities and the possibility that adversaries may attempt to insert hardware components to critical application chips and cause the chips to fail during mission or leak information. The research reported in this dissertation is focused on developing screening methods that can be employed to evaluate the chips received from fabrication facility and determine whether or not such hardware Trojans exist in the dies. The proposed techniques are based on regional and statistical analysis of transients currents measured from the chip power ports and are not only capable of detecting Trojans in a die but also can locate the position of Trojans in the chip with resolutions down to few gates. One main obstacle in all current-based test and analysis methods is the increasing rates of process and environmental variations that make the currents measured from dies of the same type of chip dramatically different from each other. Therefore, applying the statistical analysis directly to the currents measured from the chips will not be able to define thresholds for identifying Trojan-inserted chips from Trojan-free chips. A major part of the work reported in this thesis is on devising calibration methods that can be applied to the chip currents and reduce the effects of process and environmental variations. Experiments reported here demonstrate that these calibration techniques are very effective and can help determine the statistical thresholds for Trojan-free chips and make the analysis sensitive the Trojans of very small number of gates.