A fast locking digitally controlled phase-locked loop (DCPLL) with a novel frequency search algorithm is presented in this paper. The proposed frequency search algorithm can predict the target code by two predetermined codes and the two corresponding digital phase errors. To implement the proposed frequency algorithm in the PLL, a DCPLL with a constant-gain digitally controlled oscillator is developed and implemented in SMIC 0.13m 1P8M technology. Finally, the frequency acquisitions are simulated for the whole frequency range. The simulation results show that the maximum locking time of the DCPLL is four reference clock cycles.