The increasing sub-threshold leakage current levels with newer technology nodes have been identified by ITRS (2001) as one of the major fundamental problems faced by the semiconductor industry. Concurrently, the expected performance improvement and functionality integration expectations drive the continued reduction in feature size. This results in ever-increasing power per unit area and the accompanying problem of heat removal and cooling as stated in J.M.C. Stork (1995). Portable battery-powered applications, fuelled by pervasive and embedded computing, have seen tremendous growth and have reached a point where battery energy and power density can't be increased further according to T. Bell (1991). This raises the computational throughput per watt target for the future technology nodes. SRAM arrays which are used widely as a system component, such as caches and register files, in both high-performance and portable systems, are getting to be dominant power consumers because of their large capacity and area. Hence any reduction in cache energy can result in considerable overall power reduction. In this paper, we propose a novel circuit technique using depletion mode devices, to reduce the static energy of SRAM array in an on-chip cache by 90% without any performance impact.