In this paper we present a compact noise model for C-CNTFETs implemented in Verilog-A. After a brief description of the main noise sources existing in CNTFETs, which constitute a significant limitation in the design of analogue and logic CNTFETs circuits, we enhance a model, already proposed by us, considering the noise sources. The simulation results allow to determine easily the different noise contributions and the noise figure. At last the proposed noise model is compared with the Landauer model, obtaining results comparable but with an improvement in terms of run time.