In this paper we have implemented the semi-empirical compact model for CNTFETs already proposed by us to simulate typical analogue circuits and logic blocks both in SPICE, using ABM library, and in Verilog-A. The obtained results have been the same in static simulations and comparable in dynamic simulations. However using Verilog-A the simulation run time has been much shorter and the software has been much more concise and clear than schemes using ABM blocks in SPICE.