The scope of this paper is to describe the architecture of a communications line protocol for computer networks. Development and implementation details will be introduced where necessary to clarify the presentation. The need for an architecture to facilitate interprocessor communications has been a requirement to the computing industry for several years. The described line protocol was derived through an experiment with a computer network designed for heterogeneous machines, and which utilized existing software. Due to the inflexibility encountered by this approach, the architecture is being reimplemented using our own software. The line interface was defined with flexibility as the foremost requirement. The protocol developed utilizes a minimum set of line-control characters. Information is passed in the header portion of the transmitted block providing the capability of identifying a wider range of line-control and user-related functions. Error recovery has been implemented based on the same type of messages and by transferring line timing responsibilities from the hardware to the software.