The main challenge in the field of Very Large Instruction Word (VLIW) and superscalar architectures is ezploiting as much instruction-level parallelism as possible. In this paper an ezecution model which uses multiple instruction sequences and eztracts instruction-level parallelism at runtime from a set of enabled threads has been presented. A new multi-ring architecture has been proposed to support the ezeculion model. The multithreaded architecture features (i) large resident activations to improve program and data locality, (ii) a novel high-speed buger organization which ensures zero load/store stalls for the local variables of an activation, and (iii) a dynamic instruction scheduler that groups operations from multiple threads for ezecution. Initial performance evaluation studies predict that the proposed architecture is capable of ezecuting 7 concurrent operations per cycle with 8 ezecution pipes and 6 rings.