Hardware fabrication has been initiated on a test IC which has 32 channels of amplifiers, low pass anti-aliasing filters, 13-bit analog-to-digital (ND) converters per channel and a digital multiplexer. The single slope class of ND conversion is described, as are the unique variations required for incorporation on-focal plane. An IC architecture which contains an ND converter per detector channel operating at the sensor frame rate prior to digital multiplexing is described. Methods for achieving ultra low power dissipation (3 MicroWatts per channel at 1000 Hertz conversion rate) through the use of power strobing are also discussed.