Shrinkage of pixel structures and layouts for CMOS active pixel image sensors are studied. Reduction of CMOS device design rule with the scaling-law can make the pixel size small, naturally. However, using minimum design rule, quarter micron rule or sub quarter micron rule, costs expensive. Therefore, pixel size shrinkage using relatively rough design rule have been studied for reduction of the chip cost. We have already reported about small pixel structure by replacement of row-select transistor by row- select capacitor, by omission of reset transistor with forward bias reset operation, and by omission of reset transistor with pinned-buried reset channel. We have also reported about small pixel by high packing density layout named 'I-shaped cell' and its zigzag layout. However, these pixel shrinkage have some disadvantages. In this paper, we propose a novel pixel structure driven by pulse operation of drain line for row select and reset. Conventional row select structure, row select transistor or row select capacitor, is omitted by the row-select channel that contains low impurity concentration and has no gate structure. Moreover, conventional reset transistor is also replaced by reset channel structure in like manner. These structures and triple level pulse operation of drain realize quite simple pixel structure in which amplification transistor is the only gate structure. A large fill factor of 37 percent is obtained by this structure, in 5.6 micrometers X 5.6 micrometers pixel designed by 0.7 micrometers rule.