In each generation of non-volatile memory (NVM) technology, higher periphery transistor density is desired, but the operating voltage requirement tends to stay constant or rise. Technology constraints to deliver fixed voltage scaling are considered, including Lg scaling, contact size reduction and BVD (Drain breakdown voltage) improvement. Junction optimization is extending the planar technology to the 45 nm node. Asymmetric, FinFet, and recessed channel (RC) devices are considered for use in the future NVM periphery, and RC offers the best opportunity to scale device area while delivering high BVD.