Bridging faults in CMOS circuits are usually modeled as a wired-OR, wired-AND, or small fixed resistance. Real bridging faults have a resistance distribution ranging from very small to quite large. The parametric model has been proposed to handle this resistance distribution, along with table-oriented approaches that are accurate and fast. Fault simulators and a test generator have been developed using these models. Prior approaches were too slow to simulate or generate large test sets, handle large circuits, or analyze a wide variety of different test sets. We have developed PROBE, A PSEUDO-PPSFP simulator for resistive bridging faults that is significantly faster while maintaining circuit-level accuracy. We have used PROBE to analyze several large test sets on the ISCAS85 circuits in an effort to gain insight into how existing test generation approaches detect resistive bridges.