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Gate-all-around Twin Silicon nanowire SONOS Memory

descriptionPublicationkeyboard_double_arrow_right Article 01 Jun 2007Publisher:IEEEJournal:2007 IEEE Symposium on VLSI Technology
Authors: Sung Dae Suk; Kyoung Hwan Yeo; Keun Hwi Cho; Ming Li; Yun young Yeoh; Ki-Ha Hong; Sung-Han Kim; +6 Authors

doi: 10.1109/vlsit.2007.4339760

Gate-all-around Twin Silicon nanowire SONOS Memory

Abstract

We have developed gate-all-around (GAA) SONOS with ultra thin twin silicon nanowires for the first time. By using channel hot electron injection (CHEI) and hot hole injection (HHI) mechanisms, program speed of 1 mus at Vd = 2 V, Vg = 6 V and erase speed of 1 ms at Vd = 4.5 V, Vg = -6 V are achieved with 2~3 nm nanowire and 30 nm gate. Nanowire size below 10 nm dependencies on Vth shift (DeltaVth) and the program/erase (P/E) characteristics are investigated. As nanowire diameter (dnw) decreases, faster program speed and larger DeltaVth are observed.

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Powered by OpenAIRE graph
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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
23
Average
Top 10%
Top 10%
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