The author investigates and models gate-induced drain leakage (GIDL) effects over a wide variety of drain structures, including n +-As/ n --P combinations, n - implant doses ( N n-), and spacer lengths (Ls). An analytical model taking account of nm-order As doping modulation is proposed to explain the enhanced GIDL for n +-As FETs and the suppressed B-B tunneling with increasing N n- for large-tilt-angle implanted-drain devices. Band-to-defect tunneling via interface states is also simulated and found to limit device performance, as well as hot-carrier reliability, much more severely than B-B tunneling. Based on the above understanding, drain-structure design is discussed in view of both performance and reliability