In deep sub-micron VLSI chips, when several transistors in physical proximity switch simultaneously, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. As a result of lower supply voltage, transistors may slow down. Such timing faults are termed as droop faults. Modeling of droop faults and understanding their effects on the functionality and timing behavior of the circuit are yet to be fully understood. In this paper, a new model for droop faults is proposed. A simple ATPG-based procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 benchmark circuits reveal that a very high droop fault coverage can be obtained by a short sequence of test vectors.