
handle: 10045/45514
In this paper a new technique for partial product reduction based on the use of look-up tables for efficient processing is presented. We describe how to construct counter devices with pre-calculated data and their subsequent integration into the whole operation. The development of reduction trees organizations for this kind of devices uses the inherent integration benefits of computer memories and offers an alternative implementation to classic operation methods. Therefore, in our experiments we compare our implementation model with CMOS technology model in homogeneous terms.
Multiplication, VLSI technology, Look-Up Table, Specialized architecture, Arquitectura y Tecnología de Computadores
Multiplication, VLSI technology, Look-Up Table, Specialized architecture, Arquitectura y Tecnología de Computadores
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