Conventional cell delay modeling approaches calculate the propagation delay and output transition time of a CMOS logic cell, which is subjected to a noisy input waveform, by approximating this noisy waveform with a saturated ramp signal and then utilizing cell library delay look-up tables to report the output timing information. Modeling the input waveform as a saturated ramp may however result in significant error in the timing parameters of interest because the actual output waveform can be very different from the one that is implied by a simple saturated ramp input. This paper therefore presents, gcdm, a gain-based cell delay modeling technique for accurate computation of the electrical output waveform of a CMOS logic cell under a noisy input waveform. The key contribution of gcdm is that it directly calculates the output waveform of the logic cell without the need to approximate the input waveform. In effect, gcdm requires a new pre-characterization process for each cell in the library, resulting in construction of a small-signal gain lookup table. This lookup table-based approach is compatible with the existing timing analysis tools. The high accuracy of our approach is confirmed by Spice simulations.