This paper proposes a yield model for integrated circuits that includes the impact of design measures for robust design as well as traditional defect density parameters. This model is a powerful extension to common practice at silicon foundries and integrated device manufacturers. It is suitable for big digital designs, medium communication chips with analog parts, and just as well small circuits with nonvolatile memories. A new formula for parametric yield combining worst-case distance (WCD) and process capability indices enhances the conventional approach. A special yield part is introduced to account for the increasing relevance of lithography yield loss. The different parts are based on a common mathematical relation combining macroscopic and microscopic view. Simple learning functions are used for yield prognosis. The model has been implemented successfully for CMOS and embedded nonvolatile memory processes. Examples with measured yields demonstrate application and forecast quality.