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Ultra High-Speed SM2 ASIC Implementation

Authors: Zhenwei Zhao; Guoqiang Bai 0001;

Ultra High-Speed SM2 ASIC Implementation

Abstract

In this paper, we present a high-performance elliptic curve cryptographic architecture over SCA-256 prime field by introducing a one-cycle full-precision multiplier. Based on the multiplier, we give a thorough bottom-up optimization in algorithm level. The performance of the architecture is boosted by the use of a two-stage pipeline scheme, and our pipeline utilization reaches 100%. It takes only 8 cycles to perform point doubling and 12 cycles to perform point addition. Using NAF recoding of scalar k, it takes about 3333 cycles to complete the point multiplication operation. In the hardware evaluation using a 0.13 mum CMOS standard cell library, our high-performance SM2 architecture executes one point multiplication operation in 20.36 mus, which translates into more than 49000 point multiplications per second. To the best of our knowledge, our architecture offers the highest single-core performance over prime fields reported in literature up to now.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
22
Top 10%
Top 10%
Average
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