Design of an On-Chip Balun With a Minimum Amplitude Imbalance Using a Symmetric Stack Layout

descriptionPublicationkeyboard_double_arrow_right Article 01 Apr 2010Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Microwave Theory and Techniques, volume 58, pages 814-819 (issn: 0018-9480, eissn: 1557-9670,

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Authors: null Heng-Ming Hsu; null Jhao-Siang Huang; null Szu-Yuan Chen; null Szu-Han Lai;

doi: 10.1109/tmtt.2010.2041590

Design of an On-Chip Balun With a Minimum Amplitude Imbalance Using a Symmetric Stack Layout

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Abstract

This study develops a compact balun layout to minimize amplitude imbalance. Three baluns with different metal layers are fabricated using 0.13-?m CMOS technology and their imbalance performance evaluated. Measurement made using eight metal layers in coil windings at a particular layout reveal that the proposed device exhibits minimal amplitude and phase imbalance of 0.2 dB and ±0.5° with a chip outer dimension of 100 ?m .

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National Chung Hsing University
Taiwan

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